In coming years, portable devices, node sensors, battery-based electronic devices and billions of these devices will overwhelm the world and crowd with our daily life. The major concern regarding the electronic devices is about the power consumption and battery life. Power management can improve the chip's power efficiency so as to prolong the battery life and operating time. A system-on-chip consumes less power, and the sustained system lifetime will inevitably grow rapidly. A power saving mode, also called a sleep mode, is a common design approach to achieve a longer system lifetime.
Please refer to FIG. 1, which shows a system-on-chip 10 in the prior art. The system-on-chip 10 is powered by a power circuit, such as low drop-out (LDO) regulator 12. The LDO regulator 12 is powered by a battery having a voltage of 3.3 volts, and outputs a digital supply voltage to the system-on-chip 10. The system-on-chip 10 will be switched to the sleep mode when users temporarily do not need system services, but it will be switched back to the active mode when users do. During the sleep mode, the digital supply voltage provided from the LDO regulator 12 may be lowered by at least 20%, for example, from 1.2 volts to 0.9 volt as shown in FIG. 1, it indicates the system-on-chip 10 consumes 20% less power in the sleep mode compared with a normal mode.
Please refer to FIG. 2, which shows a single LDO regulator 12 operated in different modes in the prior art. The LDO regulator 12 provides the system-on-chip 10 with 1.2 volts in the normal mode, and can switch to 0.9 volt in the sleep mode. However, in fact, we need a high current capacity LDO in the normal mode, while needing a low current capacity LDO in the sleep mode Thus, it is not practical to build a single LDO to fulfil the two-end requirement, it is better to build LDO pairs.
Please refer to FIG. 3, which shows multi-level LDO regulators 11 and 13 in the prior art. For the sake of power-saving, by means of lowering the digital supply voltage, the LDO regulator 11 in a high level state can support high capacity and precision in the normal mode, the LDO regulator 13 in a low level state can support low quiescent current in the sleep mode. However, this conventional structure of a power circuit needs switches 15, 16 for each LDO regulator 11, 13 respectively, and the digital supply voltage needs to be switched between the two LDO regulators 11, 13 via switches 15, 16. When the system 14 is in the normal mode, the switches 15 and 17 conduct, and the switches 16 and 18 are cut off. The digital supply voltage may suffer from some glitches at the time the switch 15 conducts and the switch 16 is cut off, while the operations of the switches 17, 18 almost do not affect the digital supply voltage which is regulated by the LDO regulators 11, 13. Consequently, any switches arranged in the path between the LDO regulators 11, 13, may result serious glitches, and those glitches cause difficult system control issues. Thus, it is better not to have any switches along the path. Furthermore, by defining the voltage range of each LDO properly, the switchless transition can be seamless.
On the other end, for about the 5-year-life-time system powered by the battery, according to energy estimates, the digital supply voltage level needs to be aggressively lowered under the sleep mode. However, the system 14 may run under a low voltage, but a low voltage may result in a system wake-up failure. For the failure scenario, just before waking up, the digital supply voltage tends to be switched back; a level shifter 19 will receive a first signal Si having a voltage level as low as the digital supply voltage, and transform it into a second signal S2 having another level as high as the battery voltage to control the LDO regulator 11. However, not all the level shifters 19 can operate in such a wide-range supply level gap between the above low voltage level and the high voltage level if the voltage level difference is very large. The unsuccessful low-to-high translation of the level shifter 19 may result in a system failure to wake-up due to an inaccurate control signal after the level translation. Normally, a standard level will work under the 0.9 volt digital supply voltage typically, but under 0.7 volt, it will not work.
For a certain system power requirement, when the system 14 operates in the sleep mode, a standard level shifter cannot function at such a low digital supply voltage, so a specially-design level shifter may be required in order to fulfill its function. Thus, in the prior way to build an application-specific level shifter with wide operating voltage range, it may cause inefficiencies including low speed, large area, high power consumption, high cost and inefficiency of design, and these contradict our basic system assumptions which cannot be compromised.
Therefore, it is expected that different power sources can be adopted in different modes to provide the system with optimal power without switches there between, and it is also expected that a method and a device can solve the issue, a low-power system operating under wide-range supply level